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/* SPDX-License-Identifier: GPL-2.0-only */ /* * Copyright (C) 2020 Renesas Electronics Corp. */ #ifndef __DT_BINDINGS_CLOCK_R8A779A0_CPG_MSSR_H__ #define __DT_BINDINGS_CLOCK_R8A779A0_CPG_MSSR_H__ #include <dt-bindings/clock/renesas-cpg-mssr.h> /* r8a779A0 CPG Core Clocks */ #define R8A779A0_CLK_Z0 0 #define R8A779A0_CLK_ZX 1 #define R8A779A0_CLK_Z1 2 #define R8A779A0_CLK_ZR 3 #define R8A779A0_CLK_ZS 4 #define R8A779A0_CLK_ZT 5 #define R8A779A0_CLK_ZTR 6 #define R8A779A0_CLK_S1D1 7 #define R8A779A0_CLK_S1D2 8 #define R8A779A0_CLK_S1D4 9 #define R8A779A0_CLK_S1D8 10 #define R8A779A0_CLK_S1D12 11 #define R8A779A0_CLK_S3D1 12 #define R8A779A0_CLK_S3D2 13 #define R8A779A0_CLK_S3D4 14 #define R8A779A0_CLK_LB 15 #define R8A779A0_CLK_CP 16 #define R8A779A0_CLK_CL 17 #define R8A779A0_CLK_CL16MCK 18 #define R8A779A0_CLK_ZB30 19 #define R8A779A0_CLK_ZB30D2 20 #define R8A779A0_CLK_ZB30D4 21 #define R8A779A0_CLK_ZB31 22 #define R8A779A0_CLK_ZB31D2 23 #define R8A779A0_CLK_ZB31D4 24 #define R8A779A0_CLK_SD0H 25 #define R8A779A0_CLK_SD0 26 #define R8A779A0_CLK_RPC 27 #define R8A779A0_CLK_RPCD2 28 #define R8A779A0_CLK_MSO 29 #define R8A779A0_CLK_CANFD 30 #define R8A779A0_CLK_CSI0 31 #define R8A779A0_CLK_FRAY 32 #define R8A779A0_CLK_DSI 33 #define R8A779A0_CLK_VIP 34 #define R8A779A0_CLK_ADGH 35 #define R8A779A0_CLK_CNNDSP 36 #define R8A779A0_CLK_ICU 37 #define R8A779A0_CLK_ICUD2 38 #define R8A779A0_CLK_VCBUS 39 #define R8A779A0_CLK_CBFUSA 40 #define R8A779A0_CLK_R 41 #define R8A779A0_CLK_OSC 42 #endif /* __DT_BINDINGS_CLOCK_R8A779A0_CPG_MSSR_H__ */