| Server IP : 172.67.216.182 / Your IP : 172.71.124.77 Web Server : Apache System : Linux krdc-ubuntu-s-2vcpu-4gb-amd-blr1-01.localdomain 5.15.0-142-generic #152-Ubuntu SMP Mon May 19 10:54:31 UTC 2025 x86_64 User : www ( 1000) PHP Version : 7.4.33 Disable Function : passthru,exec,system,putenv,chroot,chgrp,chown,shell_exec,popen,proc_open,pcntl_exec,ini_alter,ini_restore,dl,openlog,syslog,readlink,symlink,popepassthru,pcntl_alarm,pcntl_fork,pcntl_waitpid,pcntl_wait,pcntl_wifexited,pcntl_wifstopped,pcntl_wifsignaled,pcntl_wifcontinued,pcntl_wexitstatus,pcntl_wtermsig,pcntl_wstopsig,pcntl_signal,pcntl_signal_dispatch,pcntl_get_last_error,pcntl_strerror,pcntl_sigprocmask,pcntl_sigwaitinfo,pcntl_sigtimedwait,pcntl_exec,pcntl_getpriority,pcntl_setpriority,imap_open,apache_setenv MySQL : OFF | cURL : ON | WGET : ON | Perl : ON | Python : OFF | Sudo : ON | Pkexec : ON Directory : /usr/src/linux-headers-5.15.0-142/arch/mips/include/asm/mach-cobalt/ |
Upload File : |
/* * Cobalt IRQ definitions. * * This file is subject to the terms and conditions of the GNU General Public * License. See the file "COPYING" in the main directory of this archive * for more details. * * Copyright (C) 1997 Cobalt Microserver * Copyright (C) 1997, 2003 Ralf Baechle * Copyright (C) 2001-2003 Liam Davies ([email protected]) * Copyright (C) 2007 Yoichi Yuasa <[email protected]> */ #ifndef _ASM_COBALT_IRQ_H #define _ASM_COBALT_IRQ_H /* * i8259 interrupts used on Cobalt: * * 8 - RTC * 9 - PCI slot * 14 - IDE0 * 15 - IDE1(no connector on board) */ #define I8259A_IRQ_BASE 0 #define PCISLOT_IRQ (I8259A_IRQ_BASE + 9) /* * CPU interrupts used on Cobalt: * * 0 - Software interrupt 0 (unused) * 1 - Software interrupt 0 (unused) * 2 - cascade GT64111 * 3 - ethernet or SCSI host controller * 4 - ethernet * 5 - 16550 UART * 6 - cascade i8259 * 7 - CP0 counter */ #define MIPS_CPU_IRQ_BASE 16 #define GT641XX_CASCADE_IRQ (MIPS_CPU_IRQ_BASE + 2) #define RAQ2_SCSI_IRQ (MIPS_CPU_IRQ_BASE + 3) #define ETH0_IRQ (MIPS_CPU_IRQ_BASE + 3) #define QUBE1_ETH0_IRQ (MIPS_CPU_IRQ_BASE + 4) #define ETH1_IRQ (MIPS_CPU_IRQ_BASE + 4) #define SERIAL_IRQ (MIPS_CPU_IRQ_BASE + 5) #define SCSI_IRQ (MIPS_CPU_IRQ_BASE + 5) #define I8259_CASCADE_IRQ (MIPS_CPU_IRQ_BASE + 6) #define GT641XX_IRQ_BASE 24 #include <asm/irq_gt641xx.h> #define NR_IRQS (GT641XX_PCI_INT3_IRQ + 1) #endif /* _ASM_COBALT_IRQ_H */