| Server IP : 104.21.38.3 / Your IP : 162.158.88.59 Web Server : Apache System : Linux krdc-ubuntu-s-2vcpu-4gb-amd-blr1-01.localdomain 5.15.0-142-generic #152-Ubuntu SMP Mon May 19 10:54:31 UTC 2025 x86_64 User : www ( 1000) PHP Version : 7.4.33 Disable Function : passthru,exec,system,putenv,chroot,chgrp,chown,shell_exec,popen,proc_open,pcntl_exec,ini_alter,ini_restore,dl,openlog,syslog,readlink,symlink,popepassthru,pcntl_alarm,pcntl_fork,pcntl_waitpid,pcntl_wait,pcntl_wifexited,pcntl_wifstopped,pcntl_wifsignaled,pcntl_wifcontinued,pcntl_wexitstatus,pcntl_wtermsig,pcntl_wstopsig,pcntl_signal,pcntl_signal_dispatch,pcntl_get_last_error,pcntl_strerror,pcntl_sigprocmask,pcntl_sigwaitinfo,pcntl_sigtimedwait,pcntl_exec,pcntl_getpriority,pcntl_setpriority,imap_open,apache_setenv MySQL : OFF | cURL : ON | WGET : ON | Perl : ON | Python : OFF | Sudo : ON | Pkexec : ON Directory : /usr/src/linux-headers-5.15.0-142/include/dt-bindings/gpio/ |
Upload File : |
/* SPDX-License-Identifier: GPL-2.0 */ /* * This header provides constants for binding nvidia,tegra186-gpio*. * * The first cell in Tegra's GPIO specifier is the GPIO ID. The macros below * provide names for this. * * The second cell contains standard flag values specified in gpio.h. */ #ifndef _DT_BINDINGS_GPIO_TEGRA186_GPIO_H #define _DT_BINDINGS_GPIO_TEGRA186_GPIO_H #include <dt-bindings/gpio/gpio.h> /* GPIOs implemented by main GPIO controller */ #define TEGRA186_MAIN_GPIO_PORT_A 0 #define TEGRA186_MAIN_GPIO_PORT_B 1 #define TEGRA186_MAIN_GPIO_PORT_C 2 #define TEGRA186_MAIN_GPIO_PORT_D 3 #define TEGRA186_MAIN_GPIO_PORT_E 4 #define TEGRA186_MAIN_GPIO_PORT_F 5 #define TEGRA186_MAIN_GPIO_PORT_G 6 #define TEGRA186_MAIN_GPIO_PORT_H 7 #define TEGRA186_MAIN_GPIO_PORT_I 8 #define TEGRA186_MAIN_GPIO_PORT_J 9 #define TEGRA186_MAIN_GPIO_PORT_K 10 #define TEGRA186_MAIN_GPIO_PORT_L 11 #define TEGRA186_MAIN_GPIO_PORT_M 12 #define TEGRA186_MAIN_GPIO_PORT_N 13 #define TEGRA186_MAIN_GPIO_PORT_O 14 #define TEGRA186_MAIN_GPIO_PORT_P 15 #define TEGRA186_MAIN_GPIO_PORT_Q 16 #define TEGRA186_MAIN_GPIO_PORT_R 17 #define TEGRA186_MAIN_GPIO_PORT_T 18 #define TEGRA186_MAIN_GPIO_PORT_X 19 #define TEGRA186_MAIN_GPIO_PORT_Y 20 #define TEGRA186_MAIN_GPIO_PORT_BB 21 #define TEGRA186_MAIN_GPIO_PORT_CC 22 #define TEGRA186_MAIN_GPIO(port, offset) \ ((TEGRA186_MAIN_GPIO_PORT_##port * 8) + offset) /* GPIOs implemented by AON GPIO controller */ #define TEGRA186_AON_GPIO_PORT_S 0 #define TEGRA186_AON_GPIO_PORT_U 1 #define TEGRA186_AON_GPIO_PORT_V 2 #define TEGRA186_AON_GPIO_PORT_W 3 #define TEGRA186_AON_GPIO_PORT_Z 4 #define TEGRA186_AON_GPIO_PORT_AA 5 #define TEGRA186_AON_GPIO_PORT_EE 6 #define TEGRA186_AON_GPIO_PORT_FF 7 #define TEGRA186_AON_GPIO(port, offset) \ ((TEGRA186_AON_GPIO_PORT_##port * 8) + offset) #endif